Space utilization in Integrated Circuit (IC) designs has always been an important concern. Increasing functionality is demanded within smaller spaces of the IC. Accordingly, it is highly desirable to optimization the space utilization of ICs, especially ICs that connect with external digital circuits and external analog circuits.
Up to now, the common way to optimize the area of an IC that is connectable to analog and digital circuitry was to fabricate Circuits Under Pads (CUPs) for the IC. Unfortunately, these CUPs, when positioned underneath the IC bonding pads, negatively impact the performance of the IC. Firstly, the CUPs create increased parasitics for the IC due to the close proximity of the metal bonding pads for the CUPs and the IC bonding pads and the circuits underneath. Secondly, the bonding procedure associated with utilizing the CUPs induces additional mechanical stresses.